vibeic
Official@vibeic
vibeic provides an end-to-end semiconductor design skill registry covering spec-to-RTL, analog/mixed-signal design, physical verification, FPGA debug, and tapeout sign-off.
Agent Skills by vibeic
Showing 71 vetted skills indexed across 1 GitHub repositories.
vibeicfield-agent-loop
Audits closed plugin fixes against real IC benchmarks and files converged patch bundles.
vibeicopen-benchmark-methodology
Enforces blind clean-room evaluation methodology for open RTL benchmarks like VerilogEval and CVDP.
vibeicregression-manage
Triage CI and nightly regression failures with deterministic aggregation, deduplication, severity classification, and routing.
vibeicregression-issue-fix
Enforces intake validation and fixture-first workflow for fixing Phase 1 extractor regression issues.
vibeiccheckpoint-gate
Verifies required IC design artifacts and quality thresholds before phase transitions.
vibeiceco-plan
Plan late-stage engineering change orders that minimize disruption to placed-and-routed netlists.
vibeicanalog-spec-extract
Extract analog block specifications from L1 and L5 design documents into machine-readable spec.json files.
vibeicanalog-netlist-gen
Generates SPICE netlists and testbenches from sized analog topologies with PDK device models.
vibeicfpga-led-probe-allocation
Generates FPGA LED probe allocation plans and top-level Verilog templates for board-level verification.
vibeicppa-distill
Converts a recovered PPA fix into an evidence-bound case record and draft deterministic rule.
vibeicanalog-sizing-loop
Automates closed-loop analog transistor sizing through iterative SPICE corner sweeps until all PVT specs pass.
vibeicppa-optimize
Propose bounded, reversible actuator moves that trade power, performance, and area in IC design closure loops.
vibeictestbench-gen
Generates cocotb testbenches with scoreboards, coverage, and assertions from Phase-1 L-docs.
vibeicsta-review
Triage static timing analysis reports and propose setup, hold, and skew fixes.
vibeicanalog-hw-measure
Captures oscilloscope and FPGA ADC measurements of analog blocks and grades them against spec limits.
vibeicanalog-output-verify
Verifies analog design A1-A9 outputs against deterministic gates and AI judgment checks.
vibeichw-debug-loop
Diagnoses FPGA silicon failures through bounded scope-capture and oracle bisection experiments.
vibeicanalog-hw-tuning-loop
Iterates SPICE sizing, hardware build, and measurement until analog hardware matches simulation and spec.
vibeicspec-validator
Cross-checks Datasheet, Application Note, and Spec documents for consistency and quality scores.
vibeicanalog-extraction-resim
Extracts parasitic RC from Magic layouts and re-simulates analog blocks across PVT corners.
vibeicir-drop-triage
Triage IR-drop and electromigration reports from power signoff tools into hotspot fixes.
vibeictapeout-checklist
Validates DRC, LVS, STA, IR-drop, EM, and DFT signoff status before GDS tape-out release.
vibeicflow-change-acceptance
Validates changes to shared IC design flow gates, runners, and verdict rules with bidirectional controls.
vibeichold-fix
Fixes post-CTS and post-route hold violations by inserting buffers and delay cells.
Frequently Asked Questions About vibeic
FAQPage SchemaWhat tasks can I automate using vibeic's skills?▼
You can drive the full IC flow: natural-language spec ingestion into L1-L27 JSON, spec-to-RTL authoring, testbench generation, synthesis and P&R failure diagnosis, STA/DRC/LVS/IR-drop triage, analog sizing and corner sweeps, ECO planning, FPGA debug, and final tapeout sign-off gating.
Who are vibeic's skills designed for?▼
The skills target IC design engineers and verification teams: RTL designers, analog/mixed-signal designers, physical design engineers running OpenROAD/Yosys flows, FPGA verification engineers on DE10-class boards, and agents maintaining EDA tool forks and regression farms.
How do the phase-based skills run in practice?▼
Phase 1 converts a prompt into L1-L27 JSON layer docs; Phase 2 authors and verifies RTL with testbenches; Phase 3 runs synthesis, place-and-route, and signoff. Mandatory checkpoint gates and AI spot-check verification skills run at each phase transition before advancing.
Which EDA tools and benchmarks do the skills integrate with?▼
Skills reference Yosys, OpenROAD, Magic, KLayout, Netgen, ngspice, Xyce, Spectre, HSPICE, cocotb, SymbiYosys, Verilator, Quartus SignalTap, and Voltus/RedHawk, plus benchmarks like VerilogEval, RTLLM, CVDP, and MetRex under clean-room blind evaluation methodology.
What prerequisites do vibeic's skills assume?▼
Skills assume the Vibe-IC plugin environment with its one-shot runners, paired deterministic programs (e.g., flow_compliance_check.py, gatekeeper_review.py), the vibeic-eda composed tool image, PDK access such as ihp-open-pdk, and benchmark folders for closed-loop convergence runs.