What problem does it solve? Analog block sizing traditionally requires 5-14 manual iterations of adjusting transistor W/L values, regenerating netlists, and re-running SPICE corner simulations. This Skill automates that closed loop, converging on a sizing that passes all PVT corners with deterministic pass/fail gating. ## Core Features & Use Cases - Closed-loop optimization: Orchestrates sizing, netlist generation, and SPICE corner sweeps (TT/SS/FF across -40/25/125°C) until every spec in spec.json passes, with a hard 5-iteration cap. - Deterministic convergence policy: Maps named failure modes (gain_low, bandwidth_low, phase_margin_low, noise_high, power_high, output_swing_low) to canonical sizing deltas via enforced policy scripts, plus runaway/duplicate-trial guards before each expensive corner sweep. - Structured audit outputs: Produces sizing_final.json, corner_results.json, and sizing_history.json with schema validation so results feed directly into layout and verification gates. - Use Case: After an initial sizing of an LDO in gf180 shows gain failing at the SS -40°C corner, run the loop to automatically widen the input pair, re-simulate all corners, and emit a converged sizing_final.json ready for layout. ## Quick Start Optimize the analog block by running the closed-loop sizing flow on analog/ldo_1v8 until all PVT corners pass the specs in spec.json.
