testbench-gen

Generates cocotb testbenches with scoreboards, coverage, and assertions from Phase-1 L-docs.

26|8|Updated Jun 13, 2026
One-click install
npx skills add https://github.com/vibeic/vibe-ic --skill testbench-gen-vibeic
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: testbench-gen
Source: https://github.com/vibeic/vibe-ic/tree/main/vibe-ic-marketplace/plugins/vibe-ic/skills/testbench-gen
Command: npx skills add https://github.com/vibeic/vibe-ic --skill testbench-gen-vibeic

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires cocotb, cocotb-coverage.

What problem does it solve? Writing a professional, high-coverage hardware testbench by hand is slow and error-prone, and a hand-waved skeleton can silently pass without verifying anything. This Skill derives a real functional-verification environment directly from a design's Phase-1 L-docs, so every design gets a scoreboard, functional coverage, and assertions instead of a vacuous pass. ## Core Features & Use Cases - Deterministic testbench generation: The program professional_tb_gen.py (MCP tool eda_professional_tb) reads phase1/generated_docs/L*.json and emits a cocotb testbench with clock/reset from L8/L9, a scoreboard, cocotb-coverage covergroups, an L28 coverage model, an L29 SVA assertion set, and a verification plan. - Three-tier reference-model strategy: closed-form arithmetic oracles, auto-derived bounded-latency streaming scoreboards for serial datapaths, and a clearly-marked expert reference hook for CPU/SoC/DSP classes that TestSkips until filled — never a silent vacuous pass. - Coverage review loop: Read coverage_<top>.xml and the L28 model, add directed vectors or tighten constrained-random constraints until functional bins hit 100%. - Use Case: After Phase-2 RTL is authored for a bit-serial multiplier, run Step 4 to auto-derive latency and bit order from a calibration vector and verify 208/208 vectors against the closed-form reference. ## Quick Start Ask the AI to generate a professional testbench for the current project from its Phase-1 L-docs and run the cocotb simulation.

Frequently Asked Questions about testbench-gen

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate a testbench from hardware design specifications?▼

Run the professional_tb_gen program (MCP tool eda_professional_tb) on the project; it reads the Phase-1 L-doc JSON files and emits a cocotb testbench with clock/reset, a scoreboard, functional coverage, and assertions under phase2/stage1/sim_professional.

How does the reference model work for designs without a closed form?▼

CPU, SoC, and DSP classes get a clearly-marked reference_model hook that TestSkips until filled. Write the expert oracle to expert_reference_tb.py (never the regenerated tb_<top>.py), and the loader promotes the run to dut_kind=expert_reference.

What simulators and frameworks does the generated testbench use?▼

The testbench combines cocotb as the base, cocotb-coverage for functional coverage and constrained-random stimulus, Verilator or Icarus for simulation, and an SVA bind for Verilator or SymbiYosys. Add cocotb-coverage to the runtime per the mcp-eda install guide.

Why did my custom reference model disappear after re-running Step 4?▼

The file tb_<top>.py is regenerated on every Step-4 run, so edits there are deleted. Write the oracle to the sibling expert_reference_tb.py instead; the generator loads it and regeneration cannot erase it.

Can the testbench handle bit-serial datapath designs?▼

Yes. The bounded-latency streaming scoreboard auto-derives output latency and bit order from a calibration vector, then checks every vector against the closed-form reference, closing the serial-datapath gap that simpler oracle generators defer.