What problem does it solve? Analog designs that converge in SPICE simulation often fail on real hardware due to model inaccuracies, and manually reconciling simulation, bench measurements, and spec targets is slow and error-prone. This Skill closes that loop by orchestrating a two-phase convergence process that validates SPICE results against physical measurements. ## Core Features & Use Cases - Two-phase convergence: First converges sizing in SPICE across all PVT corners, then validates on real hardware with a maximum of 3 hardware iterations. - Three-way verdict logic: Compares SPICE-vs-spec, hardware-vs-spec, and hardware-vs-SPICE discrepancy to produce CONVERGED, CONVERGED_WARNING, MODEL_INACCURACY, or BACK_TO_PHASE1 verdicts enforced by deterministic checker programs. - Human-in-the-loop bench setup: Generates FPGA stimulus, displays the component BOM and wiring diagram, and waits for user confirmation before capturing scope and ADC measurements. - Use Case: After an LDO design passes simulation, use this Skill to program a DE10-Lite FPGA, build the breadboard circuit, measure output voltage, and iterate component sizing until hardware readings fall within spec and within 20% of SPICE predictions. ## Quick Start Tune the LDO on hardware using the converged sizing in analog/ldo_1v8/sizing_final.json and verify the bench measurements against the SPICE results.
