What problem does it solve? IC design flows risk advancing to the next phase with missing deliverables or substandard quality, causing downstream failures. This Skill enforces deterministic quality gates at each phase transition so no design proceeds without passing required file and threshold checks. ## Core Features & Use Cases - Three checkpoint gates: CP1 (Phase 1→2) validates spec documents with DS≥70 and AN≥56 scores; CP2 (Phase 2→3) checks synthesis, SVA count ≥8, and DRC ≤5; CP3 (Phase 3→Production) verifies Quartus FPGA compilation and SOF generation. - Deterministic verification: Runs checkpoint_gate_check.py to enforce fixed numeric thresholds and required-file checklists, separating programmatic checks from AI-judgment items like pin-name consistency. - Compliance auditing: Validates its own sign-off output against compliance.yaml to guarantee consistent report structure across agents. - Use Case: After completing RTL design and synthesis, run the CP2 gate to confirm the netlist, GDS, DRC report, and assertion count all meet thresholds before starting FPGA verification. ## Quick Start Ask the AI to run the checkpoint gate for the current project to verify whether the design is ready to advance to the next phase.
