What problem does it solve? Running open RTL benchmarks (VerilogEval, CVDP, RTLLM, PyHDL-Eval) against an AI-driven IC design flow risks overfitting, oracle leakage, and fabricated scores. This Skill enforces a rigorous methodology so every benchmark result is honest, reproducible, and measures the general product path rather than a benchmark-tuned agent. ## Core Features & Use Cases - Single product entry enforcement: All benchmark solving must route through the standard product runner via benchmark_dispatch.py, with thin adapters allowed only for input/output translation. - Blind clean-room evaluation: Forbids reading prior runs, golden outputs, or hidden harnesses; requires fresh full-dataset runs with transcript export and blindness audits. - Program First plus independent AI review: Every candidate passes deterministic gates and a hash-bound independent AI review before official host scoring. - Evidence-backed triage and FLOOR-proof: Failures are classified as product defects, tool gaps, or dataset defects only after running the original golden RTL through the same scorer. - Use Case: When asked to run VerilogEval or CVDP and report a pass@1 score, this Skill governs the entire solve-resume-score pipeline, the per-problem four-stage attribution table, and the mandatory RESULT document with compliance gating. ## Quick Start Run the VerilogEval benchmark cleanly and produce a compliant RESULT.md with the official score, per-problem triage, and clean-room statement.
