What problem does it solve? When your RTL passes every simulation and structural gate but the burned FPGA still fails the host acceptance test, you face an open-ended trial-and-error debug loop. This Skill converts that into a bounded 7-step methodology that deterministically classifies the failure as a spec-vs-silicon discrepancy (Category B) or a pad-level synthesis artifact (Category C) and drives it to a verified PASS. ## Core Features & Use Cases - Structured evidence capture: Records baseline FAIL frames, oracle PASS verification, and oscilloscope pulse-train captures as named evidence files for reproducibility. - A/B/C decision tree: Diffs scope captures between oracle and chip SOF to route the debug effort toward either bytewise oracle dumps (spec correction with waivers) or controlled wrapper-flip experiments (pad/fan-out fixes). - Regression gating: Every fix is paired with a structural gate and a mandatory convergence audit via hw_acceptance_test_passed_check.py before Phase 2+3 closure. - Use Case: Your half-duplex protocol IC returns byte[6]=0x02 instead of 0xF2 on the connect test despite a 12/12 byte-exact BFM. The skill walks you through oracle comparison, scope capture, and wrapper bisection until the root cause is found and gated. ## Quick Start Ask the AI to run the hardware debug loop because the connect test fails with byte[6]=0x02 even though the BFM passes and the SOF is burned.
