What problem does it solve? Converting a sized analog circuit topology into a valid, simulatable SPICE netlist is error-prone: wrong body connections, missing model includes, and mismatched supply voltages are the most common causes of simulation failure. This Skill automates that translation and enforces correctness with deterministic checker programs instead of manual review. ## Core Features & Use Cases - SPICE Netlist Generation: Produces a subcircuit (.sp) and testbench (tb_*.sp) from a sizing table and topology description, with correct GF180 or SKY130 device instantiation. - Deterministic Compliance Gates: Runs checker programs that catch PMOS/NMOS body-connection errors, missing model includes, wrong include order, floating nodes, and supply/PDK mismatches. - Automated .meas Generation: Derives measurement statements directly from spec.json via a generator program rather than hand-authoring them. - Use Case: After sizing a two-stage op-amp for the gf180 PDK, invoke this Skill to emit the subcircuit netlist and a testbench with DC/AC stimulus, then pass it to ngspice simulation at Step A4. ## Quick Start Ask the AI to generate a SPICE netlist and testbench for your sized analog block using the gf180 PDK, then run the compliance gate to verify the output.
