What problem does it solve? Analog design automation can mark steps PASS or WAIVED without confirming real correctness, since analog quality is rarely binary. This Skill closes that gap by spot-checking corner-simulation coverage, hardmacro completeness, and hardware-vs-SPICE data fidelity after the analog one-shot runner finishes. ## Core Features & Use Cases - Deterministic gate orchestration: Runs per-step checker programs for A3 netlists, A4 corner sweeps, A5 layouts, A6 per-block DRC/LVS, A7 post-layout resim, A8 hardmacro LEF/GDS outlines, and A9 hardware correlation. - AI judgment layer: Applies residual checks programs cannot make, such as silicon-realistic specs, topology-to-spec consistency, and outlier patterns in corner data. - Escalation routing: Directs failures to the right follow-up loop, such as analog-sizing-loop for corner failures or analog-hw-tuning-loop for hardware correlation drift. - Use Case: After /vibe-ic-analog reports PASS on an amplifier block, run this Skill to confirm the 9-corner sweep has real margins, the LEF outline matches the GDS bounding box, and HW-vs-SPICE error stays under 5%. ## Quick Start Ask the AI to review the analog outputs of the current project and verify the A4 corner sweep and A8 hardmacro results.
