What problem does it solve? When verifying a chip on a DE10-Lite-class FPGA board with no oscilloscope or SignalTap, the on-board LEDs are the only observability. This Skill removes the guesswork of assigning signals to LEDs by codifying four probe modes and producing a documented top-level template. ## Core Features & Use Cases - Four probe modes: instantaneous, pulse-stretched, sticky, and byte-display, each matched to a signal's timing behavior so a 30 fps webcam can actually capture the state. - Comment-table template: emits a Verilog top module with an LED PROBE TABLE comment mapping each LED to its signal and expected behavior per test stage. - Deterministic lint integration: pairs with fpga_led_probe_lint.py, which flags anti-patterns like instantaneous-on-pulse, mode-mix-without-table, sticky-without-reset-clear, and shared-pin-vs-QSF. - Use Case: A fresh agent must verify a chip on a DE10-Lite using only LEDR[9:0] and a USB webcam; the Skill allocates sticky flags for tx_done and cmd_decoded plus a byte-display column for the last response byte, then validates the result with the lint and compliance gate. ## Quick Start Allocate the ten LEDs on my DE10-Lite board to probe my UART DUT's tx_done, cmd_decoded, and last response byte signals, and generate the FPGA top template with the probe table.
