Triage static timing analysis reports and propose setup, hold, and skew fixes.
npx skills add https://github.com/vibeic/vibe-ic --skill sta-review-vibeic
Please help me install this Agent Skill. Skill: sta-review Source: https://github.com/vibeic/vibe-ic/tree/main/vibe-ic-marketplace/plugins/vibe-ic/skills/sta-review Command: npx skills add https://github.com/vibeic/vibe-ic --skill sta-review-vibeic
High-intent search queries and answers about installing and using this skill.
Run the sta_triage_classify.py program with the endpoints JSON, WNS, and TNS values. It categorizes every violating endpoint into cell-delay, net-delay, logic-depth, clock-skew, or hold buckets and returns a fix strategy per category, such as upsizing, buffer insertion, or RTL pipelining.
A common cause is a PnR script that runs only repair_timing -hold without set_wire_rc, repair_design, and repair_timing -setup, leaving STA optimistic. The pnr_timing_repair_completeness_check.py gate fails any script missing that chain.
Yes. It requires SS and FF corner coverage and audits corner-to-liberty resolution, so a run that reads one library three times is flagged as SINGLE_CORNER_ONLY rather than recorded as multi-corner closure. DRV queries via report_check_types are also verified.
A self-loop with one register has a minimum period equal to the full combinational cone delay, and retiming preserves register count per cycle, so the bound is invariant. The fix, when the spec allows, is splitting the recurrence into a multi-cycle round across two or more clocked sub-stages.
No. Measured cases show pre-PnR gains reversing after routing because added area becomes wire delay, and OpenROAD already resizes post-placement. Always re-run the post-route A/B on the shipped SPEF before adopting any synthesis QoR knob.
amoslee2026Automate OpenSTA multi-corner timing analysis and parse results into JSON.
KishoreDamamDiagnose STA setup/hold violations by mapping report_timing fields to the slack equation.
tangyangchao578-artAnalyze dynamic and static power, IR drop, and EM violations in IC designs.
chuanseng-ngAutomate multi-corner timing analysis and sign-off for chip designs.
