What problem does it solve? After analog layout, parasitic resistance and capacitance can silently degrade circuit performance, and a flawed extraction recipe can produce a parasitic-free netlist that makes pre-vs-post comparison report a false 0% degradation. This Skill performs post-layout parasitic extraction and re-simulation, then deterministically compares pre-layout vs post-layout specs to catch layout-induced regressions before tape-out. ## Core Features & Use Cases - Deterministic extraction recipe generation: Emits and validates the Magic parasitic-RC TCL via programs/magic_extract_spice_emit.py, enforcing correct command ordering (extract all, extresist, ext2spice) that Magic 8.3 requires. - Netlist audit before re-simulation: Verifies the extracted SPICE netlist actually contains R/C elements, distinguishing full RC from C_ONLY depth and failing honestly when extraction produced nothing. - Pre-vs-post comparison gate: Runs analog_pre_vs_post_layout_check.py to compute per-metric per-corner degradation against canonical thresholds (≤20% OK, >20% WARNING, >30% NEEDS_RELAYOUT). - Use Case: After finishing Magic layout of an LDO, ask whether the layout hurt bandwidth; the Skill extracts parasitics, re-simulates all PVT corners, and reports that UGB dropped 33%, routing the block back to layout. ## Quick Start Run post-layout extraction and re-simulation on my analog block and tell me whether the layout degraded any specs compared to the pre-layout corner results.
