What problem does it solve? AI-generated and hand-written RTL often contains latch inference, width mismatches, reset hygiene issues, and cross-module encoding mismatches that pass simulation but fail in synthesis or on FPGA hardware. This Skill runs a deterministic audit pipeline that scores RTL 0-10 and produces a structured review report before simulation or tape-in. ## Core Features & Use Cases - Deterministic multi-auditor pipeline: Runs rtl_hygiene_lint, reset_discipline_check, and rtl_precheck_gate via rtl_review_aggregate.py, aggregating findings into six categories with a pytest-pinned scoring rubric. - Cross-module interface checks: Detects gray-code vs binary encoding mismatches, TX data content errors (CRC bit-reversal, status byte fields), and TX/RX counter approach violations. - FPGA-specific blocking rules: Rejects Quartus-unsafe ROM initialization patterns that silently synthesize to all-zero on Intel/Altera targets. - Use Case: A designer shares a directory of SystemVerilog files and asks "is this synthesizable?" The Skill runs the aggregate program, emits rtl_review.md and rtl_review.json with a score and verdict, then hands off to /rtl-repair on FAIL or /checkpoint-gate on PASS. ## Quick Start Review all RTL files in my project directory and tell me the score, verdict, and which lint or synthesis hazards need fixing before tapeout.
