rtl-specification-consistency-checker

What problem does it solve?

This Skill automates the critical process of verifying that hardware Register-Transfer Level (RTL) implementations accurately match their high-level functional and timing specifications, catching costly design errors early.

Core Features & Use Cases

• Requirement Extraction: Parses hardware specifications to identify and formalize behavioral requirements.
• RTL Mapping: Maps these requirements to corresponding signals, logic, and states within the RTL code.
• Consistency Checking: Systematically verifies if the RTL behavior satisfies each requirement, classifying them as satisfied, violated, underspecified, or uncheckable.
• Violation Reporting: Generates detailed reports for any discrepancies, including root cause analysis and suggested fixes.
• Use Case: When a hardware design team suspects their Verilog implementation of a complex bus protocol might not fully adhere to the protocol's timing or functional rules, they can use this Skill to systematically check every specified rule against the RTL code.

Quick Start

Use the rtl-specification-consistency-checker skill to check the consistency between the specification document 'design_spec.md' and the RTL code in the directory '/path/to/rtl/project'.