readable-hls-generator

Generate, review, annotate, and validate readable AMD/Xilinx Vitis HLS C/C++ kernels.

29|5|Updated May 8, 2026
One-click install
npx skills add https://github.com/Eriemon/hls-generator --skill readable-hls-generator-eriemon
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: readable-hls-generator
Source: https://github.com/Eriemon/hls-generator
Command: npx skills add https://github.com/Eriemon/hls-generator --skill readable-hls-generator-eriemon

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) and assets (resource) components.

What problem does it solve? Turning a hardware behavior contract into readable, validated Vitis HLS C/C++ kernels requires coordinating pragmas, interfaces, testbenches, configuration, and tool reports, which is error-prone when done manually. ## Core Features & Use Cases - Contract-driven generation: Create readable HLS C/C++ kernels, interface-aware testbenches, and structured specs from a confirmed HLS JSON contract covering pipeline behavior, streamability, and interface profiles. - Review and annotation: Inspect HLS sources, pragmas, and reports, or perform comment-only rewrites with Chinese semantic comments guarded by AST/token fingerprint comparison against a baseline. - Static and tool-based validation: Run static readiness checks locally and execute Vitis csim/cosim or remote board acceptance when a Vitis toolchain or approved remote server is available. - Use Case: Provide a confirmed contract for an AXI4-Stream FIR filter, then generate the kernel and testbench, add Chinese semantic comments, and validate through Vitis HLS cosim on a remote server. ## Quick Start Ask your AI assistant to use Readable HLS Generator to create a readable Vitis HLS kernel from your confirmed behavior contract, for example a vector-scale kernel with an AXI4 interface.

Frequently Asked Questions about readable-hls-generator

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate a Vitis HLS kernel from a specification?▼

Provide a confirmed HLS JSON contract with pipeline behavior, streamability, interface family, and confirmation notes, then use the Create route to scaffold the spec and generate readable HLS C/C++ kernel artifacts with an interface-aware testbench.

How do I validate HLS code without a local Vitis installation?▼

Static validation runs locally and reports static_only=true without claiming tool execution. For real tool evidence, the workflow issues a remote toolchain request so you can select a configured erie-remote-ssh server that has Vitis HLS available.

Can this skill generate Verilog or SystemVerilog directly?▼

No, handwritten Verilog and SystemVerilog generation is explicitly out of scope. The skill only produces HLS C/C++ sources, headers, testbenches, .cfg files, vectors, and reports, though HLS-generated RTL issues traced back to Vitis HLS code are in scope.

How are comment-only changes to HLS code verified?▼

Comment-only rewrites are validated with an AST guard that compares non-comment token fingerprints and normalized AST fingerprints against a baseline artifact tree. Clang is the primary AST provider, with tree-sitter and pycparser as fallbacks.

What Vitis HLS versions and interfaces are supported?▼

The skill targets AMD/Xilinx Vitis HLS with guidance based on the Vitis HLS 2024.2 script guide, and ships templates for AXI4, AXI4-Stream, m_axi burst, DATAFLOW, and task-level parallelism patterns. Remote acceptance supports version selection when multiple Vitis installs are detected.