What problem does it solve? Converting an algorithm already written in C, C++, or SystemC into hardware by hand is slow and error-prone. This Skill guides the High-Level Synthesis (HLS) flow that lowers software algorithmic descriptions into synthesizable RTL, then enforces the same deterministic lint and review gates that hand-written RTL must pass. ## Core Features & Use Cases - Guided HLS workflow: Cleans source code (removing pointers, dynamic allocation, recursion), selects interfaces (AXI-Stream, AXI-Lite, BRAM), and applies pragmas such as PIPELINE, UNROLL, DATAFLOW, and ARRAY_PARTITION. - C/RTL co-simulation and PPA reporting: Co-simulates against golden test vectors and produces a directive log with latency, throughput, and area estimates. - Mandatory deterministic gates: Runs rtl_review_aggregate, rtl_hygiene_lint, and reset_discipline_check on HLS-emitted RTL, plus a compliance audit, before any result is accepted. - Use Case: You have a C++ matrix-multiply or DSP filter reference implementation and need a Verilog block for an FPGA or ASIC. The Skill produces the annotated source, HLS tool script, and a PPA report, then hands the RTL off to review and testbench generation. ## Quick Start Ask the assistant to convert your C++ algorithm into synthesizable RTL using HLS with a target clock period and interface constraints.
