rtl-property-inference
CommunityInfer RTL properties & generate SVA.
AuthorArabelaTso
Version1.0.0
Installs0
System Documentation
What problem does it solve?
This Skill automates the generation of formal correctness properties (SystemVerilog Assertions - SVA) directly from Verilog/SystemVerilog RTL code, reducing manual effort and improving hardware verification.
Core Features & Use Cases
- Automated Property Inference: Identifies common hardware design patterns (handshakes, state machines, pipelines) and infers relevant safety, liveness, and fairness properties.
- SVA Generation: Outputs well-formed SVA code with natural-language explanations for each inferred property.
- Use Case: When integrating a new RTL module, use this Skill to automatically generate assertions that capture its intended behavior, ensuring it adheres to expected protocols and invariants.
Quick Start
Use the rtl-property-inference skill to infer properties from the provided Verilog file 'my_module.v'.
Dependency Matrix
Required Modules
None requiredComponents
references
💻 Claude Code Installation
Recommended: Let Claude install automatically. Simply copy and paste the text below to Claude Code.
Please help me install this Skill: Name: rtl-property-inference Download link: https://github.com/ArabelaTso/Skills-4-SE/archive/main.zip#rtl-property-inference Please download this .zip file, extract it, and install it in the .claude/skills/ directory.
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