Erie
Community@eriemon
Erie publishes FPGA-focused skills for synthesizable Verilog-2001 RTL generation and readable Vitis HLS creation, review, annotation, validation, and debug.
Agent Skills by Erie
Showing 2 vetted skills indexed across 2 GitHub repositories.
Frequently Asked Questions About Erie
FAQPage SchemaWhat tasks can I complete with Erie's skills?▼
Erie’s skills cover two hardware design jobs: turning written hardware requirements into synthesizable Verilog-2001 RTL, and creating, reviewing, annotating, or validating readable Vitis HLS/high-level synthesis sources. They fit FPGA RTL construction and HLS debug preparation, not general software delivery.
Who should use Erie's Verilog and HLS skills?▼
The best fit is FPGA engineers, RTL designers, hardware architects, and verification staff who already read timing, datapath, interface, and synthesis constraints. Students learning Verilog-2001 or Vitis HLS can also use the outputs as structured reference material.
How do I run or install these skills in practice?▼
The manifest does not define packages, commands, runtimes, or environment setup. Practically, a user supplies hardware requirements for Verilog generation or opens HLS sources for review, annotation, validation, and debug inside the relevant FPGA design context.
Are Erie's skills open source or free to use?▼
No license, price, or redistribution terms are provided in the supplied manifest, so cost and open-source status remain unknown. Treat the skills as unlicensed until the repository or registry entry states explicit permissions, obligations, and commercial-use limits.