ascendc-hardware-tiling

Classify the operator (elementwise, broadcast, reduction, indexed, matmul-like, fused) and reuse one tiling skeleton per class. Add a mode field to TilingData chosen on the host from dtype, rank, stride, and broadcast semantics, then branch on mode at the outer level in device code.

Use core_num = min(max_cores, ceil_div(total, min_work_per_core)), then work_per_core = ceil_div(total, core_num). Each core computes core_start and core_len = min(work_per_core, total - core_start), returns early if core_start >= total, and skips tail copy when tail_len is zero.

GM/UB transfers should use 32B-aligned tile sizes. For non-32B-aligned data, use DataCopyPad or a dedicated tail path, and offset hot LocalTensors by at least 32B to avoid UB bank conflicts.

Queue bugs usually come from unbalanced pairing: every AllocTensor needs a FreeTensor and every EnQue a matching DeQue, including in tail branches. Also avoid excess PipeBarrier calls, which destroy overlap unless a real data dependency exists.

No. Query chip parameters through the SDK when available, or centralize constants in one helper if the seed provides them. Scattered hardcoded values make kernels fragile across hardware variants.

Generic index mapping with div/mod and multi-level stride computation should only be a fallback path. Prefer specialized modes like same-shape flattening or last-dim broadcast for performance, keeping generic mode for full semantic coverage.