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triton-ascend-a5-api

Documents Cube/Vector co-programming APIs for Triton kernels on Atlas A5 hardware.

6|1|Updated Apr 19, 2026
Search Tags:#synchronization#triton#ascend#npu#kernel programming#cube vector#fixpipe
One-click install
npx skills add https://github.com/xchang1121/op-autoresearch --skill triton-ascend-a5-api-xchang1121
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: triton-ascend-a5-api
Source: https://github.com/xchang1121/op-autoresearch/tree/main/skills/triton-ascend/fundamentals/triton-ascend-a5-api
Command: npx skills add https://github.com/xchang1121/op-autoresearch --skill triton-ascend-a5-api-xchang1121

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve? Writing high-performance kernels on Atlas A5 (Ascend950) hardware requires coordinating Cube and Vector cores through specialized Buffer Language and Ascend Language APIs, and misuse of synchronization or alignment rules causes deadlocks, data races, or silent corruption. ## Core Features & Use Cases - Buffer Language Reference: Covers bl.alloc, to_buffer, to_tensor, and subview for managing UB/L1/L0 on-chip buffers with constexpr shape constraints. - Ascend Language Reference: Documents al.scope, fixpipe, sync_block_set/wait, sub_vec_id, and copy, including PIPE enums, DMA modes, and alignment rules. - Use Case: When writing a fused attention or GEMM kernel where Cube computes tl.dot results and Vector applies softmax/bias/relu epilogues, use this reference to correctly wire fixpipe transfers and cross-core synchronization with balanced event IDs. ## Quick Start Ask the agent to write an A5 kernel where Cube performs a matmul and Vector applies a softmax epilogue using fixpipe and sync_block_set/wait synchronization.

Frequently Asked Questions about triton-ascend-a5-api

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I synchronize Cube and Vector cores in Triton Ascend kernels?▼

Use al.sync_block_set and al.sync_block_wait with matching sender, receiver, and event_id parameters. Pair PIPE_FIX with PIPE_V for fixpipe data-ready signaling, and ensure set/wait calls are count-balanced to avoid deadlocks.

How do I move matmul results from L0C to UB on Ascend A5?▼

Call al.fixpipe inside a cube scope, passing the tl.dot result as source and a UB buffer created with bl.to_buffer as destination. Choose a DMA mode like NZ2ND and respect alignment rules such as 8-element alignment for float32.

Does al.fixpipe work on Ascend hardware other than A5?▼

No, al.fixpipe and al.copy are exclusive to Atlas A5 (Ascend950) hardware. Kernels targeting earlier Ascend chips must use different data movement mechanisms.

Why does my A5 kernel deadlock when using sync_block_set?▼

Deadlocks occur when set/wait pairs are not count-balanced or when different shared resources reuse the same event_id. Assign distinct event IDs (0-15) per resource and add prefree/postwait pairs in ping-pong buffer schemes.

What are the alignment constraints for fixpipe on Ascend A5?▼

For float32, the last dimension must be 8-aligned, and 32-aligned when using ROW_SPLIT or COLUMN_SPLIT dual-destination modes. For float16/bfloat16, the last dimension must be 16-aligned, and NZ2DN mode requires 8-alignment on the first dimension.

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