lvs-triage

Parse the LVS report into categories: unmatched instances, unmatched nets (shorts and opens), device parameter mismatches, and property mismatches. Check the top-3 root causes first — a missing net label, a missing via between metal layers, or a wrong PDK device variant — then fix each mismatch at its reported layer and coordinate.

For digital standard-cell designs, compare the post-P&R Verilog netlist against the synthesis netlist with netgen -batch lvs using the PDK setup file such as GF180MCU's libs.tech/netgen/setup.tcl. For device-level sign-off, extract the GDS to SPICE with Magic ext2spice and load the standard-cell SPICE library into the schematic side.

Netgen device-level LVS is the stronger check for sign-off because it matches transistors directly. Yosys equiv_simple/equiv_induct is structural LEC that returns unproven cells for technology-mapped standard cells, a known tool limitation rather than a real netlist mismatch.

This happens when Magic's GDS extraction emits a portless .subckt with an empty port list, leaving netgen nothing to anchor name matching against. Fix it by promoting labels to ports with Magic port makeall on the PDK port-purpose layer, or seed ports from the DEF PINS section.

Yes. A portless extracted top subcircuit can produce a vacuous match that a naive wrapper reports as PASS. Run a sign-off guard that raises on portless extracted subcircuits, and verify against netgen's real verdict lines like Circuits match rather than a boolean flag.

KLayout LVS targets GDS extraction versus SPICE schematic for analog and mixed-signal designs, not digital standard-cell flows. Magic LVS cannot extract a layout netlist when no PDK tech file exists, such as for GF180MCU, so netgen netlist comparison is used instead.