gf

What problem does it solve?

This Skill automates the entire SystemVerilog development lifecycle, from initial planning and code generation to verification and debugging, ensuring working RTL code is delivered efficiently.

Core Features & Use Cases

• End-to-End RTL Development: Handles all tasks from concept to verified code.
• Agent-Driven Workflow: Leverages specialized agents for planning, coding, verification, and debugging.
• Use Case: Requesting "implement and verify a UART controller" will trigger planning, code generation, linting, simulation, and debugging if necessary, delivering a fully functional and verified module.

Quick Start

Use the gf skill to create a FIFO with a valid/ready interface and a self-checking testbench.