assertion-design

What problem does it solve?

SystemVerilog Assertions (SVAs) provide a formal, executable specification layer for RTL behavior, but teams often struggle to organize and reuse these properties while keeping them separate from the design. This skill advocates a specification-first approach, enabling precise, RTL-agnostic properties and a clean binding mechanism to DUTs.

Core Features & Use Cases

• Specification-first design: write properties in SVAs that are RTL-agnostic and attach them via separate assertion modules (bind) rather than embedding in DUT.
• Clear organization: dedicated locations for timing specs (sim/assertions/spec/), functional assertions (sim/assertions/functional/), and bindings (sim/assertions/bind/).
• Scenarios: define timing requirements, protocol properties (e.g., AXI/UART), and formal properties for transaction sequences to guide rigorous verification.

Quick Start

• Set up the directory structure as described above: sim/assertions/spec/, sim/assertions/functional/, sim/assertions/bind/.
• Create sample files: sim/assertions/spec/uart_timing_spec.sva, sim/assertions/functional/Uart_Tx_Assertions.sv, and sim/assertions/bind/bind_Uart_Tx.sv; compile with ENABLE_ASSERTIONS and verify properties with a bound DUT.