Design and review Verilog/SystemVerilog FSMs with three-process structure and SVA assertions.
npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill fsm-design
Please help me install this Agent Skill. Skill: fsm-design Source: https://github.com/KishoreDamam/VLSI-agkit/tree/main/.agent/skills/fsm-design Command: npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill fsm-design
This Skill helps you write and review Verilog/SystemVerilog FSMs that synthesize cleanly without unintended latches, illegal states, or broken handshakes.
case assignments with default-before-case patterns, and ensure deterministic reset behavior.Use the fsm-design skill when you are implementing or reviewing a SystemVerilog FSM and you want the pattern that prevents latches, handles all states, and includes a practical timeout and SVA assertions.
High-intent search queries and answers about installing and using this skill.
Prevent latch inference in SystemVerilog FSMs by using default assignments before the `case` statement and adopting a three-process structure to separate state registers, next-state logic, and outputs.
Handle illegal states in Verilog finite state machines by implementing deterministic reset behavior and defining safe default transitions within your state encoding logic to ensure robust recovery.
Add SVA assertions to verify FSM handshake protocols by writing properties for legal-state checks, liveness, no-deadlock conditions, and handshake invariants to catch issues early in simulation and formal verification.
Yes, a three-process FSM structure supports one-hot, binary, and gray state encoding choices, improving linting and reviewability while maintaining correct next-state and output logic separation.
Implement timeout counters for FSM wait states by integrating a separate programmable timeout counter module that safely transitions the state machine out of stalled handshake conditions.
Incomplete case assignments during linting usually indicate missing default branches; using default-before-case patterns ensures all states are handled and prevents unintended latch synthesis.
dtsongReview Verilog, SystemVerilog, and VHDL RTL designs for security vulnerabilities.
babywormGenerate SystemVerilog assertion bind files with naming, clock/reset guards, and sv2v guidance.
KishoreDamamWrite SystemVerilog assertions for formal verification of RTL control paths.
kos3nzPrototype separate LOGIC.md and UI.md branches to validate designs before coding.