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rtl-security-review

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Secure RTL designs against vulnerabilities.

Software Engineering#security#vulnerability analysis#rtl#verilog#hardware design#vhdl
Authordtsong
Version1.0.0
Installs0

System Documentation

What problem does it solve?

This Skill identifies and mitigates security vulnerabilities within Register Transfer Level (RTL) designs, ensuring hardware integrity and preventing exploits.

Core Features & Use Cases

  • Vulnerability Detection: Analyzes Verilog, SystemVerilog, and VHDL for access control bypasses, insecure FSM transitions, timing leaks, and unintended data paths.
  • Policy Enforcement: Verifies adherence to security policies and trust boundary definitions.
  • Use Case: A hardware security engineer can use this skill to perform a thorough security audit on a new cryptographic module's RTL code before tape-out, identifying critical flaws like a bypassable access control gate.

Quick Start

Review the attached Verilog file 'secure_module.v' for security vulnerabilities.

Dependency Matrix

Required Modules

None required

Components

references

💻 Claude Code Installation

Recommended: Let Claude install automatically. Simply copy and paste the text below to Claude Code.

Please help me install this Skill:
Name: rtl-security-review
Download link: https://github.com/dtsong/claude-code-windows-setup/archive/main.zip#rtl-security-review

Please download this .zip file, extract it, and install it in the .claude/skills/ directory.
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