What problem does it solve? After every netlist transformation — synthesis, DFT insertion, clock gating, or ECO — you must prove the result is functionally identical to the golden RTL. This Skill drives Logic Equivalence Checking (LEC) through MCP-EDA's Yosys equiv mode and enforces the verdict with a deterministic gate program, so a PASS can never be claimed from log inspection alone. ## Core Features & Use Cases - Deterministic LEC execution: Invokes eda_lvs in yosys_equiv mode to compare golden vs revised netlists, returning proven/unproven equiv-cell counts and writing reports/lec.json. - Anti-vacuous verdict gate: programs/lec_equivalence_check.py independently re-parses the report and returns rc=0 only when equivalence is true, compared points are non-zero, and no unproven or non-equivalent points remain. - Mismatch triage workflow: Maps key points, reports unmapped registers, and classifies mismatches as real functional changes, benign reset differences, or X-propagation issues. - Use Case: After inserting scan chains into a synthesized design, run LEC between the pre-DFT and post-DFT netlists with test pins constrained, then gate the sign-off on the deterministic checker before proceeding to place-and-route. ## Quick Start Ask the AI to run an equivalence check between your golden RTL netlist and the post-synthesis netlist for your top module using the sky130 PDK, then confirm the gate program returns PASS.
