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ascendc-tiling-design

Guides tiling design for Ascend C operators across Reduction, Elementwise, and Broadcast patterns.

6|1|Updated Apr 19, 2026
Search Tags:#tiling#broadcast#npu#kernel optimization#reduction#ascend c#ub buffer
One-click install
npx skills add https://github.com/xchang1121/op-autoresearch --skill ascendc-tiling-design-xchang1121
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: ascendc-tiling-design
Source: https://github.com/xchang1121/op-autoresearch/tree/main/skills/ascendc/fundamentals/ascendc-tiling-design
Command: npx skills add https://github.com/xchang1121/op-autoresearch --skill ascendc-tiling-design-xchang1121

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve? Designing multi-core partitioning and UB (Unified Buffer) slicing for Ascend C kernels is error-prone: developers must choose the right algorithm per operator family, compute UB budgets against hardware limits, and handle alignment, dtype, and boundary cases correctly. ## Core Features & Use Cases - Scenario Routing: Decision trees route Reduction (AR/ARA, FullLoad/Split), Elementwise, and Broadcast operators to the correct tiling strategy based on shape, axes, and chip (DAV_2201 vs DAV_3510). - Algorithm Library: Covers Welford online statistics, Group Reduce cross-core reduction, dichotomy summation for precision, and index-tracking ArgMax/ArgMin variants. - UB Budget Formulas: Provides concrete buffer equations, tmpBufSize computation, multi-core split parameters, and tiling struct field conventions. - Use Case: When implementing a LayerNorm or Softmax kernel on Ascend 910B, use this Skill to decide between AR-FullLoad and AR-ColSplit, compute chunk sizes, and plan double-buffered queues. ## Quick Start Ask the assistant to design the tiling plan for a ReduceSum kernel with shape [A1, R] on Ascend 910B, including multi-core split and UB buffer allocation.

Frequently Asked Questions about ascendc-tiling-design

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I design tiling for an Ascend C reduction operator?▼

First collapse axes into A (kept) and R (reduced) dimensions, then check A0: if A0=1 use AR mode with Level 2 Reduce APIs, otherwise use ARA mode with Pattern::Reduce::RA. Then decide FullLoad versus split loading based on whether the data fits in UB.

How to choose between Welford and TwoPass for variance reduction?▼

Use TwoPass when data fully resides in UB and you can afford two sequential reduction passes. Use Welford online when data is split into chunks, since it computes mean and variance in a single streaming pass and saves one round of IO.

What is the UB capacity limit on Ascend 910B for tiling?▼

Ascend 910B/B3 provides 192KB of UB, 910B4 provides 128KB, and Ascend 950 provides 248KB. All buffer planning including input queues, calc buffers, and double buffering must fit within this budget.

When should I use NDDMA broadcast versus UB Broadcast on Ascend?▼

NDDMA broadcast is only available on DAV_3510 (Ascend 950) and performs hardware-based broadcast during GM-to-UB copy with stride=0. On DAV_2201, use the UB Broadcast static interface or DataCopyPad plus Copy and GatherMask fallback.

Why does my Ascend C reduction lose precision on large inputs?▼

Sequential accumulation causes large values to swallow small ones in floating point. Use dichotomy (binary-tree) summation so similar-magnitude values add first, or use FP32 intermediate accumulation for FP16/BF16 inputs.

How do I track indices during ArgMax reduction in Ascend C?▼

For AR-FullLoad use ReduceMax with calIndex=true. For ARA patterns, replace Pattern::Reduce::RA with a per-row Compare plus Select loop, storing indices as float because DAV_2201 Select does not support int32 outputs, then cast to int32 at the end.

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