verilog-lint
CommunityLint Verilog RTL with Verilator and Verible.
System Documentation
What problem does it solve?
Lint and validate Verilog/SystemVerilog (RTL/HDL) code using Verilator and Verible. Trigger when Claude generates RTL, writes Verilog or SystemVerilog, checks HDL syntax, lints hardware description code, fixes Verilog errors, or when they mention modules, always blocks, wire/reg/logic declarations, clocks, resets, FSMs, synthesis, flip-flops, or any digital hardware design topic.
Core Features & Use Cases
- Semantic linting with Verilator (--lint-only -Wall) to catch undeclared signals, width mismatches, undriven/unused nets, and blocking/non-blocking issues.
- Style linting with Verible (verible-verilog-lint) to enforce naming conventions, whitespace, and port alignment.
- End-to-end lint loop with up to 3 automatic iterations to produce a clean result, surfacing remaining issues with a diagnostic table if needed.
Quick Start
Provide the Verilog or SystemVerilog code you want linted and I will run Verilator and Verible to produce a clean RTL design.
Dependency Matrix
Required Modules
None requiredComponents
Standard package💻 Claude Code Installation
Recommended: Let Claude install automatically. Simply copy and paste the text below to Claude Code.
Please help me install this Skill: Name: verilog-lint Download link: https://github.com/morganp/dotfiles/archive/main.zip#verilog-lint Please download this .zip file, extract it, and install it in the .claude/skills/ directory.
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