uvm-verification

What problem does it solve?

This Skill provides a structured methodology for building scalable, reusable UVM verification environments for SystemVerilog testbenches, addressing the complexity of coordinating tests, environments, agents, drivers, monitors, sequences, and scoreboards.

Core Features & Use Cases

• Standardized naming conventions: Guidelines for tests, environments, agents, drivers, monitors, and scoreboards to ensure consistency across projects.
• Component templates: Reusable templates and patterns for driver, monitor, agent, environment, and test components to accelerate verification development.
• Project organization guidance: Clear file/layout recommendations for simulating and organizing UVM artifacts in large-scale projects.
• Use Case: Adopt a consistent UVM architecture to enable team collaboration and easier maintenance of complex AXIUART_RV32I verification environments.

Quick Start

Start by reviewing the UVM verification methodology and create a minimal axiuart_top testbench structure following the naming conventions outlined.