SystemVerilog RTL Design
CommunitySystemVerilog RTL design patterns and templates.
Authorcodejunkie99
Version1.0.0
Installs0
System Documentation
What problem does it solve?
This skill provides ready-to-use SystemVerilog RTL design patterns, synthesis guidelines, and templates to standardize and accelerate hardware coding.
Core Features & Use Cases
- Pattern Library: Reusable modules, FSM templates, parameterized designs, and common RTL blocks following modern SystemVerilog practices.
- Synthesis Guidance: Clear guidelines for avoiding latches, using always_ff/always_comb, and reliable timing.
- Real-World Scenarios: Use when prototyping modules, pipelines, CDCs, or when you need maintainable, synthesizable SV code.
Quick Start
Ask the Skill to provide a ready-to-use SystemVerilog RTL design snippet for a parameterized FIFO or FSM.
Dependency Matrix
Required Modules
None requiredComponents
Standard package💻 Claude Code Installation
Recommended: Let Claude install automatically. Simply copy and paste the text below to Claude Code.
Please help me install this Skill: Name: SystemVerilog RTL Design Download link: https://github.com/codejunkie99/gateflow-cli/archive/main.zip#systemverilog-rtl-design Please download this .zip file, extract it, and install it in the .claude/skills/ directory.
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