SystemVerilog Development

What problem does it solve?

This Skill helps hardware/software engineers write clean, synthesizable SystemVerilog RTL by applying modern conventions and safe coding patterns.

Core Features & Use Cases

• Always block conventions: Use always_ff, always_comb, and appropriate reset patterns to improve reliability and synthesizability.
• Signal types and widths: Use logic, typedefs, and explicit widths to avoid ambiguity.
• FSM and handshaking patterns: Provide robust FSM templates and valid/ready handshakes.
• Port declarations and RTL structure: ANSI-style, parameterized modules with clear interfaces.
• Use Case: Imagine guiding an engineer to convert a dated RTL design into modern SV with clean state machines and robust resets.

Quick Start

Ask the system to generate a minimal 8-bit counter module in SystemVerilog using always_ff and a reset.