rtl-sim-debug-pcie-dummy

To debug PCIe LTSSM and TLP issues during RTL simulation, this skill provides a domain-specific template that plugs into a parent rtl-sim-debug workflow, applying targeted context to diagnose failures across controller, PIPE PHY, and flow-control layers.

A domain sub-skill for PCIe RTL verification is a structured template that links domain-specific triggers and context fields to a parent debug workflow, enabling targeted diagnostics for link training, DLLP, and TLP failures.

To customize a PCIe RTL debug sub-skill, rename the template to target your specific subsystem and flesh out the Markdown body by adding domain playbooks, references, and scripts to deploy it in a real debugging workflow.

Yes, this template covers PCIe controller and PIPE PHY scope including link training and flow-control messages, but it serves as a demo for integration rather than implementing a real debug capability out of the box.

This RTL debug template covers the PCIe protocol stack including the controller, PIPE PHY, LTSSM, TLP, DLLP, and flow-control messages to illustrate domain-specific diagnostic integration.

Your PCIe RTL debug workflow needs domain-specific triggers to ensure the parent debug skill activates the correct operational instructions and loads the necessary context fields when PCIe events and messages are detected.