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rtl-p5s-protocol-verify

Generate SVA assertions and simulation checks for AXI, AHB, and APB protocol violations.

43|9|Updated Feb 25, 2026
Search Tags:#simulation#assertions#rtl#protocol-verification#sva#axi-ahb-apb
One-click install
npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p5s-protocol-verify
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-p5s-protocol-verify
Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/rtl-p5s-protocol-verify
Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p5s-protocol-verify

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

Protocol conformance for RTL bus interfaces (AXI, AHB, APB) is critical for reliable SoC integration; this skill validates those interfaces using formal SVA assertions and simulation-based protocol checking to catch violations early.

Core Features & Use Cases

  • Formal SVA-based protocol assertion generation for AXI, AHB, and APB interfaces.
  • Simulation-based protocol checking with violation reporting and artifact generation (protocol-report.md and formal/{bus}_assertions.sv).
  • Use Case: verify protocol compliance during RTL development and prior to SoC integration, and investigate violations surfaced in simulation.

Quick Start

Run the protocol orchestrator to generate AXI/AHB/APB protocol assertions and perform simulation checks, producing a protocol-report and assertion files.

Frequently Asked Questions about rtl-p5s-protocol-verify

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I verify AXI, AHB, and APB protocol compliance in RTL?▼

Verify AXI, AHB, and APB protocol compliance by generating formal SVA assertions and running simulation-based checks to identify bus interface violations during RTL development or SoC integration.

What is SVA-based protocol checking for RTL bus interfaces?▼

SVA-based protocol checking uses SystemVerilog assertions to formally validate RTL bus interface behavior, detecting AXI, AHB, and APB protocol violations early in the development cycle.

How do I generate SVA assertions for AXI and AHB interfaces?▼

Generate SVA assertions for AXI and AHB interfaces by running a protocol orchestrator that produces formal assertion files and a comprehensive protocol violation report.

Can I use formal verification to investigate RTL simulation violations?▼

Yes, use formal SVA checks to investigate RTL bus protocol violations reported during simulation, applying targeted assertion generation to validate AXI, AHB, and APB conformance.

What outputs do I get from RTL protocol verification?▼

RTL protocol verification outputs include a protocol-report.md detailing identified violations and formal assertion files formatted as formal/{bus}_assertions.sv for AXI, AHB, and APB interfaces.

When should I run protocol conformance checks on RTL designs?▼

Run protocol conformance checks during RTL development and prior to SoC integration to catch AXI, AHB, and APB bus interface violations early and ensure reliable system assembly.

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