rtl-equivalence-checker

What problem does it solve?

This Skill automates the verification of functional equivalence between two Register-Transfer Level (RTL) designs, ensuring that modifications or optimizations do not alter the intended behavior.

Core Features & Use Cases

• Functional Equivalence Checking: Compares two Verilog RTL designs to determine if they behave identically.
• Difference Analysis: Identifies and categorizes differences as cosmetic (e.g., naming) or semantic (e.g., logic changes).
• Counterexample Generation: Produces minimal traces to demonstrate functional discrepancies.
• Use Case: After refactoring a hardware module for better readability, use this Skill to confirm that the refactored version performs exactly the same as the original under all conditions.

Quick Start

Run the equivalence check between 'design_a.v' and 'design_b.v' using the default settings.