rtl-coding-standards

What problem does it solve?

This Skill codifies and enforces SystemVerilog RTL coding standards across projects to improve readability, reliability, and maintainability.

Core Features & Use Cases

• Timescale Directive: Ensures every RTL file starts with a valid timescale.
• Declaration Placement: Mandates declarations at the beginning of modules or blocks.
• Consistent Reset & Always Blocks: Standardizes reset behavior and the correct always_ff/always_comb usage.
• Naming & Style: Enforces consistent naming conventions for modules, signals, and interfaces.
• Use Case: A design team adopts these standards to reduce review comments and speed up integration of RTL modules.

Quick Start

Apply the rtl-coding-standards to new RTL modules by aligning your module headers to the prescribed patterns and referencing the project docs for examples.