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rtl-coding

Guide engineers to write clean, synthesizable SystemVerilog RTL code.

2|1|Updated Apr 6, 2026
Search Tags:#verification#lint#rtl#cdc#systemverilog#hdl#verilog
One-click install
npx skills add https://github.com/tangyangchao578-art/icer_skill_package --skill rtl-coding
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-coding
Source: https://github.com/tangyangchao578-art/icer_skill_package/tree/main/skills/rtl-coding
Command: npx skills add https://github.com/tangyangchao578-art/icer_skill_package --skill rtl-coding

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Provides a structured approach for engineers to produce clean, synthesizable and maintainable RTL code, reducing debugging time and design risk.

Core Features & Use Cases

  • Comprehensive module skeletons, naming conventions, reset strategies, lint-ready patterns, CDC guidelines, and power-aware coding.
  • Step-by-step workflows for starting new RTL blocks, performing code reviews, and verifying designs.
  • Practical templates and templates that accelerate design, verification, and debugging tasks.

Quick Start

Create a new SystemVerilog module following the RTL coding guidelines and apply the standard skeleton, naming conventions, and lint checks.

Frequently Asked Questions about rtl-coding

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I write synthesizable SystemVerilog with proper reset strategies and CDC guidelines?▼

Write synthesizable SystemVerilog by applying consistent reset styles, using non-blocking assignments, and following strict CDC guidelines for cross-domain handling to ensure clean, maintainable RTL code.

What are the best practices for RTL coding to pass lint checks and reduce design risk?▼

Best practices to pass lint checks include enforcing default-case coverage, maintaining consistent reset styles, and ensuring proper cross-domain handling, which directly reduces debugging time and design risk.

How do I structure a new SystemVerilog module skeleton for maintainable RTL development?▼

Structure a new SystemVerilog module by applying standard module skeletons, adhering to naming conventions, and integrating lint-ready patterns alongside power-aware coding templates from the start.

Does this RTL coding approach work for both design and verification workflows?▼

Yes, this approach supports both design and verification by providing step-by-step workflows for starting new blocks, performing code reviews, and verifying designs using practical templates.

Why do I need default-case coverage and power-aware patterns in my HDL design?▼

You need default-case coverage and power-aware patterns in HDL design to optimize power consumption, prevent latch inference, and enforce comprehensive lint checks across the verification process.

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