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remote-dc-synthesis

Synthesize RTL into a gate-level netlist on a remote Linux server via SSH using Synopsys Design Compiler.

4|4|Updated Apr 8, 2026
Search Tags:#ssh#rtl#workflow-template#remote-synthesis#design-compiler#tsmc65nm
One-click install
npx skills add https://github.com/232322336666/vibe_circuit_deisgn.skill --skill remote-dc-synthesis
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: remote-dc-synthesis
Source: https://github.com/232322336666/vibe_circuit_deisgn.skill/tree/main/remote-dc-synthesis
Command: npx skills add https://github.com/232322336666/vibe_circuit_deisgn.skill --skill remote-dc-synthesis

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Synthesize RTL into a gate-level netlist on a remote Linux server using Design Compiler by reusing a verified template to ensure correct setup and consistent results.

Core Features & Use Cases

  • Template-driven remote synthesis: Copy from a verified example and modify TOP_DESIGN_NAME to start a new DC project.
  • Configurable constraints and scripts: Update cons/top_cons.tcl and .synopsys_dc.setup to tailor timing and library paths for the design.
  • Result analysis via reports: Generate QoR, area, timing, and power reports to drive design decisions.

Quick Start

Copy the DC workflow from the verified template, adjust TOP_DESIGN_NAME and cons/top_cons.tcl for your design, then run the remote synthesis.

Frequently Asked Questions about remote-dc-synthesis

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I run Design Compiler synthesis on a remote Linux server?▼

Run remote Design Compiler synthesis by copying a verified template, updating TOP_DESIGN_NAME and cons/top_cons.tcl, then executing the synthesis workflow via SSH to generate a gate-level netlist.

What is template-driven remote synthesis and when do I need it?▼

Template-driven remote synthesis reuses a verified example to configure Synopsys Design Compiler on a remote server, ensuring correct setup and consistent gate-level netlist results for new RTL designs.

Can I use this remote synthesis workflow for TSMC 65nm designs?▼

Yes, you can apply this remote synthesis workflow to TSMC 65nm designs by configuring library paths and timing constraints in .synopsys_dc.setup and cons/top_cons.tcl.

How do I configure timing constraints for remote DC synthesis?▼

Configure timing constraints by copying the verified template and modifying cons/top_cons.tcl to tailor timing and library paths specifically for your design's requirements.

What reports does Design Compiler generate after remote synthesis?▼

Design Compiler generates QoR, area, timing, and power reports after remote synthesis, providing outputs to analyze results and drive design decisions for your gate-level netlist.

Do I need SSH access to run remote RTL synthesis with Design Compiler?▼

Yes, SSH access is required to connect to the remote Linux server and execute the Design Compiler synthesis workflow, enabling constraint creation and results analysis.

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