multicore

What problem does it solve?

Engineers designing systems with multiple CPU cores need a structured approach to configure, coordinate, and secure cross-core execution and communication. This Skill provides a cohesive set of patterns for Zephyr SMP, AMP with OpenAMP/RPMsg, IPC patterns, and dynamic extension loading.

Core Features & Use Cases

• SMP configuration and thread affinity for multi-core SoCs
• OpenAMP/RPMsg-based cross-core communication between homogeneous or heterogeneous cores
• IPC patterns for efficient data sharing and synchronization
• LLEXT dynamic extensions to load modular functionality at runtime
• Use Case: A dual-core MCU handling real-time control on Core 0 and image processing on Core 1 with secure extension loading

Quick Start

Configure SMP on a dual-core SoC by enabling CONFIG_SMP=y and CONFIG_MP_NUM_CPUS=2 in prj.conf. Set up an OpenAMP/RPMsg channel for cross-core messaging and choose an IPC pattern (e.g., mailboxes or shared memory) for data exchange. If dynamic extension loading is required, enable LLEXT (CONFIG_LLEXT=y) and provide an ELF extension path.