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moai-vivado

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End-to-end FPGA flow with Vivado & XSim.

Software Engineering#synthesis#rtl#bitstream#fpga#vivado#xsim#verilog
Authorhnabyz-bot
Version1.0.0
Installs0

System Documentation

What problem does it solve?

This skill provides a structured approach to automate and orchestrate Xilinx Vivado FPGA development tasks, covering RTL simulation with XSim, synthesis, implementation, and bitstream generation.

Core Features & Use Cases

  • End-to-end FPGA flow: Automate simulation, synthesis, place-and-route, and bitstream generation for Artix-7 devices.
  • Toolchain integration: Coordinates xvlog/xelab/xsim and Vivado batch flow for scalable CI workflows.
  • Use Case: When validating a SystemVerilog design, run sim workflows, synthesize for target hardware, and produce a bitstream in a repeatable script.

Quick Start

Install Vivado 2024.2 or newer, then run the provided TCL scripts to perform simulation and synthesis tasks without GUI.

Dependency Matrix

Required Modules

None required

Components

Standard package

💻 Claude Code Installation

Recommended: Let Claude install automatically. Simply copy and paste the text below to Claude Code.

Please help me install this Skill:
Name: moai-vivado
Download link: https://github.com/hnabyz-bot/gate_drv/archive/main.zip#moai-vivado

Please download this .zip file, extract it, and install it in the .claude/skills/ directory.
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