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gf-architect

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Map and document SystemVerilog codebases.

Software Engineering#architecture#documentation#codebase analysis#rtl#systemverilog#hardware design
AuthorRedClaus
Version1.0.0
Installs0

System Documentation

What problem does it solve?

This Skill automates the process of understanding, mapping, and documenting complex SystemVerilog codebases, significantly reducing the time and effort required for onboarding to new RTL projects or analyzing existing ones.

Core Features & Use Cases

  • Codebase Mapping: Generates a comprehensive map of modules, hierarchy, signals, and dependencies.
  • Architecture Documentation: Creates detailed documentation including hierarchy diagrams, signal flow, clock domains, and FSMs.
  • Use Case: When joining a new RTL project, use this Skill to quickly generate a visual map and documentation of the entire codebase, allowing you to understand module interactions and data flow within minutes.

Quick Start

Use the gf-architect skill to map the current SystemVerilog codebase.

Dependency Matrix

Required Modules

None required

Components

scriptsreferences

💻 Claude Code Installation

Recommended: Let Claude install automatically. Simply copy and paste the text below to Claude Code.

Please help me install this Skill:
Name: gf-architect
Download link: https://github.com/RedClaus/cortex/archive/main.zip#gf-architect

Please download this .zip file, extract it, and install it in the .claude/skills/ directory.
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