skills.rest
Paradicat
ParadicatCOMMUNITY
Explore all skills by this author →
GitHub

fast-elaborator

Analyze Verilog/SystemVerilog RTL for gate count, logic depth, and flip-flop count using Yosys and OpenSTA.

1|1|Updated Jun 15, 2023
Search Tags:#synthesis#rtl#ppa#yosys#opensta#timing analysis
One-click install
npx skills add https://github.com/Paradicat/demo --skill fast-elaborator
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: fast-elaborator
Source: https://github.com/Paradicat/demo/tree/main/agent_pack/skills/fast-elaborator
Command: npx skills add https://github.com/Paradicat/demo --skill fast-elaborator

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) components.

What problem does it solve?

This Skill provides rapid Power, Performance, and Area (PPA) analysis for RTL designs without requiring a full Electronic Design Automation (EDA) flow.

Core Features & Use Cases

  • Quick Synthesis: Synthesizes RTL designs using Yosys for immediate analysis.
  • PPA Estimation: Offers gate counts, flip-flop counts, and logic depth analysis.
  • Hierarchy Navigation: Allows exploration of the design's hierarchical structure.
  • Use Case: Quickly estimate the gate count and critical path logic depth of a Verilog module before committing to a lengthy synthesis run.

Quick Start

Load the design file 'design.v' with 'my_module' as the top-level module.

Frequently Asked Questions about fast-elaborator

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I estimate RTL gate count and logic depth without running a full EDA flow?▼

You can estimate RTL gate count and logic depth without a full EDA flow by running Verilog or SystemVerilog files through Yosys for quick synthesis and OpenSTA for immediate timing analysis.

Can I perform PPA estimation on SystemVerilog files using Yosys and OpenSTA?▼

Yes, PPA estimation is supported for SystemVerilog files. The Skill uses Yosys to synthesize the RTL and OpenSTA to extract metrics like flip-flop counts and critical path logic depth.

What is the best way to quickly check the flip-flop count of a Verilog module before full synthesis?▼

The best way to check flip-flop count is to load the Verilog file and specify the top-level module to run a rapid synthesis pass, which provides immediate flip-flop and gate count metrics.

Does this fast PPA analysis tool explore the hierarchical structure of an RTL design?▼

Yes, the fast PPA analysis tool explores the hierarchical structure of the RTL design, allowing you to navigate the design hierarchy alongside extracting area and timing estimates.

When should I use rapid RTL PPA estimation instead of a complete synthesis run?▼

Use rapid RTL PPA estimation when you need quick feedback on gate counts, flip-flop counts, and logic depth before committing to a lengthy full EDA synthesis run.

What inputs do I need to start timing analysis on my RTL design?▼

To start timing analysis, you need to provide your Verilog or SystemVerilog design file and specify the top-level module name to initialize the quick synthesis process.

Related Skills

Explore More Software Engineering Skills→
londeylondey
18

claude-skill-verilog

Enforce consistent Verilog and SystemVerilog coding style for Verilator linting and Yosys synthesis.

Community
Intermediate
AnsteorraAnsteorra
6

badge-list-consistency

Enforce identical permission checks between notification badge counts and linked list views.

Official
Intermediate
Aryaman9999Aryaman9999
6

open-verifier

Automate end-to-end Verilog/SystemVerilog verification with linting, simulation, and reporting.

Community
Advanced
chuanseng-ngchuanseng-ng
180

logic-synthesis

Synthesize RTL to gate-level netlists with SDC validation and LEC verification.

Community
Advanced