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Domain Layer

Automate electronics build pipelines to generate Gerbers, BOMs, and PCB layouts.

3.6k|225|Updated Dec 19, 2023
Search Tags:#build-pipeline#exporters#pcb#kicad#netlists#muster#electronics
One-click install
npx skills add https://github.com/atopile/atopile --skill domain-layer
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: Domain Layer
Source: https://github.com/atopile/atopile/tree/main/.claude/skills/domain_layer
Command: npx skills add https://github.com/atopile/atopile --skill domain-layer

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

The Domain Layer Skill encapsulates the electronics-specific build logic and workflows needed to transform software-defined graphs into manufacturing artifacts such as Gerbers, BOMs, and PCB layouts.

Core Features & Use Cases

  • Build orchestration: Centralized pipeline management using the Muster task runner.
  • Exporters: Provides netlist formatting, PCB export, BOM generation, and documentation artifacts.
  • Layout synchronization: Keeps manual PCB changes in sync while updating from code.
  • Use Case: A hardware project uses ato.yaml to generate Gerbers and BOMs automatically during CI.

Quick Start

Run the standard build pipeline from a project directory (where ato.yaml lives): ato build

Frequently Asked Questions about Domain Layer

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I automate PCB layout generation and BOM export from code?▼

Automate PCB layout generation and BOM export by running the `ato build` pipeline, which uses the Muster task runner to transform `.ato` or `.py` configurations into Gerbers, BOMs, and PCB layouts automatically.

What is the Muster task runner and how does it orchestrate electronics build pipelines?▼

The Muster task runner is a centralized pipeline management mechanism that orchestrates electronics build steps, registering tasks to transform software-defined graphs into manufacturing artifacts like Gerbers and BOMs.

Can I synchronize manual PCB changes when updating layouts from code?▼

Yes, you can synchronize manual PCB changes using the layout synchronization feature, which keeps manual updates in sync while applying new PCB exports generated from your `.ato` or `.py` configurations.

Does this build pipeline support netlist formatting and KiCad exports?▼

Yes, the build pipeline supports netlist formatting and KiCad exports through dedicated exporters, allowing you to generate manufacturing artifacts and synchronize PCB layouts with KiCad from your code configurations.

How do I generate Gerbers and BOMs automatically during CI for an atopile project?▼

To generate Gerbers and BOMs automatically during CI, run `ato build` in your project directory containing `ato.yaml` to trigger the Muster task runner and execute the registered build steps for manufacturing artifacts.

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